distributed systems · hpc · low-level engineering

Ojima Abraham

software engineer · researcher · open source contributor
session://ojima/profile
$ whoami
> software engineer @ kalshi · open source contributor
$ cat interests.txt
> distributed systems, GPU computing, CDC, low-level programming
$ git log --oneline -3
> a1b2c3d feat: chronos v1.1.0 released on PyPI
> d4e5f6g feat: jikan CDC — building in public
> g7h8i9j fix: stacked-seds radial photometry pipeline
// open-source

Open Source

Projects I've built and contribute to.

Recent contributions
// publications

Publications & Research

Selected publications spanning mathematics and astrophysics, with the full record available on Google Scholar.

2025
CECILIA: The Mass-Metallicity Relation of Low-Mass Galaxies at Cosmic Noon
arXiv preprint (arXiv:2512.00162), submitted Nov 2025
Menelaos Raptis, Gwen C. Rudie, Ryan F. Trainor, Noah S. J. Rogers, Allison L. Strom, Nathalie A. Korhonen Cuestas, Caroline von Raesfeld, Ye Lin, Ojima Ojodomo Abraham, Christopher Chapman, Charles C. Steidel, Michael V. Maseda
Uses ultra-deep JWST/NIRSpec spectroscopy to study low-mass galaxies at z~2-3.
2023
Perspectives Through a Two-Slit Camera
The Mathematical Intelligencer, Volume 45, pp. 299-306 (Springer)
Annalisa Crannell, Ojima Abraham, Jihang Dai, Yike Gong, Rebecca McClain, Nithya Ramaswamy, Charles Reisner, Evan Shinn, Shen Wang
Department of Mathematics, Franklin & Marshall College. Open access under CC BY 4.0.
// the-spec

The WAVE Specification

The WAVE Specification

Wide Architecture Virtual Encoding

v0.2 — Working Draft (Revised)

A vendor-neutral instruction set architecture for general-purpose GPU computation. Defines an abstract execution model, register model, memory model, structured control flow, and instruction set derived from eleven hardware-invariant primitives identified across NVIDIA, AMD, Intel, and Apple GPU architectures spanning 16 microarchitectures. Follows the thin abstraction principle: defines what a compliant implementation must do, not how. Validated by a reference implementation with 102 passing conformance tests.

Status: Working Draft Last Updated: March 23, 2026 License: Apache 2.0 Authors: Ojima Abraham, Onyinye Okoli

Table of Contents

1. Introduction 1.1 Purpose 1.2 Scope 1.3 Design Principles 1.4 Relationship to Other Standards 1.5 Changes from v0.1 2. Execution Model 2.1 Overview 2.2 Thread Hierarchy 2.3 Thread Identifiers 2.4 Core Resources 2.5 Execution Guarantees 2.6 Dispatch 3. Register Model 3.1 General-Purpose Registers 3.2 Sub-Register Access 3.3 Register Pairs 3.4 Special Registers 3.5 Predicate Registers 3.6 Allocation and Occupancy 4. Memory Model 4.1 Memory Spaces 4.2 Local Memory Details 4.3 Device Memory Details 4.4 Memory Ordering 4.5 Atomic Operations 5. Control Flow 5.1 Structured Control Flow 5.2 Uniform Branches 5.3 Divergence and Reconvergence 5.4 Minimum Divergence Depth 5.5 Per-Wave Control Flow State 6. Instruction Set 6.1 Integer Arithmetic 6.2 Bitwise Operations 6.3 Floating-Point (F32) 6.4 Floating-Point (F16) 6.5 Floating-Point (F64, Optional) 6.6 Type Conversion 6.7 Comparison and Select 6.8 Local Memory Operations 6.9 Device Memory Operations 6.10 Atomic Operations 6.11 Wave Operations 6.12 Synchronization 6.13 Control Flow Instructions 6.14 Matrix Multiply-Accumulate (Optional) 7. Capability System 7.1 Required Constants 7.2 Optional Capabilities 7.3 Matrix MMA Parameters 7.4 Query Mechanism 8. Binary Encoding 8.1 Overview 8.2 Base Instruction Format (48-bit) 8.3 Extended Instruction Format (80-bit) 8.4 Opcode Map 9. Conformance 9.1 Required Behavior 9.2 Implementation-Defined Behavior 9.3 Undefined Behavior 9.4 Conformance Testing A. Full Opcode Table B. Vendor Mapping Reference C. Revision History
// about

About & Contact

Software engineer at Kalshi. Expert in distributed systems, systems performance, low-level programming, compiler and interpreter design, parallel programming, and high-performance computing. Based in Brooklyn, New York.